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A*STAR and Soitec Launch Joint Program to Develop a New Layer Transfer Process for Advanced Packaging

New cost competitive wafer-to-wafer layer transfer process delivers low power, increased yield and higher interconnection density and speed

Source : SOITEC - Singapore and Bernin (Grenoble), Mar. 26, 2019 – 

The Agency for Science, Technology and Research's (A*STAR) Institute of Microelectronics (IME) and Soitec (Euronext Paris), a world leader in designing and manufacturing innovative semiconductor materials, announce the launch of a joint program to develop and integrate a new layer transfer process within advanced wafer level multi-chip packaging techniques. Based on the combination of IME's Fan-Out Wafer Level Packaging (FOWLP) and 2.5D Through Silicon Interposer (TSI) technologies with Soitec's Smart Cut(TM) technology, the new cost competitive process offers higher performance, energy efficiency and increased product yield.

Advanced packaging is used in many of today's systems on chip (SOCs) for servers, high-end mobile, industrial, and automotive applications, and involves various approaches for combining semiconductor chips into packages to reduce costs, improve power efficiency, and provide efficient heat dissipation. By 2022, the advanced packaging market segment is expected to triple to two million wafer starts for mid- to high-end applications[1]. The rising complexity of today's chips with growing numbers of smaller and smaller transistors and circuits requiring high I/O counts is driving collaborative innovation across the advanced packaging process community focused on identifying cost effective solutions for manufacturing, and increased data bandwidth to support hand-held, cloud and edge computing applications.

One of the standard processes in advanced packaging involves using a full silicon wafer for the layer transfer process, which can cost up to 3 cents/mm2. Soitec will partner with IME over the next three years to evaluate the use of its Smart Cut(TM) technology on IME's advanced packaging platforms FOWLP and 2.5D TSI, with the objective to integrate a new layer transfer process as a key step in future generations of packaging techniques. This new process targets improved performance, lower power consumption and reduced production costs by eliminating the need to consume a full silicon wafer. IME will also conduct tests to evaluate the reliability and robustness of the newly developed process, which will help Soitec to determine its long-term viability.

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