TSMC to tape out first 5nm chip design in 1H19

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

DIGITIMES, Taipei, Jan. 23, 2019 – 

Despite its dim business and industry outlook this year, Taiwan Semiconductor Manufacturing Company (TSMC) continues to make progress in the development of sub-7nm process technologies with plans to move a newer 5nm EUV process to volume production by 2020 well on track.

TSMC CEO CC Wei disclosed at the company's recent investors meeting that the foundry is scheduled to start taping out 5nm chip designs later in the first half of 2019. TSMC is on track to move its 5nm process incorporating EUV lithography technology to volume production in the first half of 2020, according to Wei.

"All applications that are using 7nm today will adopt 5nm," said Wei. "We expect more applications in HPC to adopt N5."

TSMC regards its 5nm process, dubbed N5, as a long-lived node, same as its 7nm, 16nm and 28nm processes. Wei disclosed that TSMC's 7nm chip customers are "all" engaged with the foundry at N5, without giving further details, such as the number of tape-outs.

Wei noted that TSMC's 7nm chip client portfolio is "growing stronger" as more chip designs for applications such as HPC and automotive demand the process. "Customer tape-outs activities at N7 continue to be strong despite the cautious macro outlook," Wei said.

 Back