New DRAM Architecture Targets Edge AI

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

Etron Technology revealed a brand-new DRAM architecture called "Reduced Pin Count" (RPC) DRAM, which uses only half the pins to drive miniaturization and cut cost...

LAS VEGAS, Jan. 17, 2019 – 

Over the last few decades, the DRAM industry has single-mindedly followed a single roadmap in pursuit of higher-density memories, beginning with asynchronous DRAM and evolving to DDR5 synchronous DRAM.

In contrast, Etron Technology (Hsinchu, Taiwan) revealed at the Consumer Electronics Show that instead of following the conventional path, it's charting an alternative roadmap with a brand-new DRAM architecture called "Reduced Pin Count" (RPC) DRAM.

Etron CEO Nicky Lu argued that the proposed RPC DRAM, which uses only half the pins, can both drive miniaturization and cut cost. He pitched PRC DRAM as ideal for miniaturized wearable devices and end-point AI subsystems. With DDR4, many companies designing small wearable devices today must buy more than they need, Lu added. "For many designers of small systems, DDR4 is an overkill."

 Back