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Zeno Demonstrates Scalability of World's Smallest SRAM Bitcell Technology to FinFET Technology Node at IEDM Conference


1- /2-Transistor SRAM Technology Demonstrated at Standard FinFET Process Technology

Sunnyvale, CA, December 5, 2018 – Zeno Semiconductor, a Silicon Catalyst Portfolio Company, demonstrated the scalability of its novel 1-transistor/2-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology to FinFET technology node at the IEDM Conference. The results from 14nm and 16nm FinFET technology nodes from multiple foundries follow previous implementation of Bi-SRAM technology in 28nm technology node.

Zeno’s 1-transistor/2-transistor Bi-SRAM uses a single transistor as the memory bitcell and is therefore 3x-5x smaller than conventional SRAMs which use 6-transistor bitcells (6T-SRAM). Another key announcement is that the Bi-SRAM technology can be fabricated in baseline FinFET process without any process modifications. This is in contrast to other emerging memory technologies, such as magnetic random access memory (MRAM) or resistive random access memory (RRAM), which requires new materials.

“Given the amount of chip area occupied by SRAM in the state-of-the-art SoCs, 1-transistor SRAM is very attractive. Therefore, it is exciting to see that Zeno has demonstrated the scaling of the 1-transistor SRAM using FinFET devices. Since it was done without process modifications, it paves the way to achieve more functional chips with the same cost of integrated circuits manufacturing,” said Dr. Runzi Chang, Deputy Director of Foundry Technology at Marvell Semiconductor, Inc.

This is echoed by Dr. Victor Moroz, a Fellow at Synopsys, “We have previously used Synopsys’ Sentaurus TCAD to simulate the 1-transistor SRAM in FinFET structure, so the silicon demonstration is somewhat expected. However, the previously simulated 1-transistor SRAM utilizes a buried n-well layer. The new development without a buried n-well layer is significant as it makes the technology fully compatible with standard foundry process.”

TARGET MARKETS INCLUDE INTERNET OF THINGS (IOT), MOBILE, CONSUMER, HPC, NETWORKING, AND ARTIFICIAL INTELLIGENCE (AI)

The CMOS process compatibility and the small memory size makes Zeno Bi-SRAM technologies as the ideal embedded memory technology. Average die area occupied by embedded memory in a System-on-a-Chip (SoC) is projected to reach >70% in 2019 according to Semico Research, with new architectures (for example in AI applications) see the largest year-to-year increase in the embedded memory content.

BUSINESS MODEL AND AVAILABILITY

Zeno’s business model is to license the 1-transistor Bi-SRAM and 2-transistor Bi-SRAM technologies and IP to semiconductor companies and foundries. Licensees can implement their own memory macros, or they can contract with Zeno to do so.

The technology is available for customer engagement today; please contact Zeno for more details.

ABOUT ZENO SEMICONDUCTOR

Zeno Semiconductor, Inc. (www.zenosemi.com) develops and licenses novel memory and logic technologies which provide innovative paths to scaling semiconductor devices. The memory and logic technologies are manufacturable on mainstream CMOS and FinFET fabrication processes with no new materials or equipment, and with no changes to any of the existing libraries and IP. Zeno currently has been awarded more than 50 patents.

Zeno Demonstrates Scalability of World's Smallest SRAM Bitcell Technology to FinFET Technology Node at IEDM Conference

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