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Analog Bits to demonstrate Low Power SERDES at TSMC's Open Innovation Platform Ecosystem Forum

Santa Clara, CA -- October 3, 2018 - Analog Bits (www.analogbits.com), an industry leading provider of low-power mixed-signal IP (Intellectual Property) solutions, with a low picojoule-per-bit SERDES macro, will demonstrate this licensable IP core running on TSMC's 12nm process geometry. Implementations of this same multi-protocol SERDES architecture are available on a variety of TSMC process nodes and support speeds of up to 25Gb/s. The combination of high performance and low power make this an excellent solution for short reach, chip-to-chip applications while support for multiple protocols means that the same SERDES architecture can be used in silicon devices requiring interfaces like SAS and PCIe. Analog Bits' products are used by numerous customers, ranging from current industry leaders such as Microchip to new companies like Wave Computing. Products include other mixed-signal IP such as PLLs, IOs and Sensors and are ported to TSMC's advanced manufacturing nodes - including 7nm.

WHAT:

WHEN: October 3, 2018



SERDES IP Cores

WHERE: TSMC 2018 Open Innovation Platform Ecosystem Forum
Booth: 308
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054

About Analog Bits: Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is a leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O's as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon and design kits supporting processes from 0.35-micron to 7nm, Analog Bits has an outstanding heritage of "first-time-working" with foundries and IDMs.

Analog Bits to demonstrate Low Power SERDES at TSMC's Open Innovation Platform Ecosystem Forum

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