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Intilop to Showcase their 40G-10G TCP-UDP Acceleration Technology and Solutions at MIT's Lincoln Labs

MILPITAS, Calif., Sept. 24, 2018 -- Intilop, Inc., a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators like Full TCP-UDP-IGMP & other Mega-IP Cores, System-Solutions since 2009, plan to showcase their 40G-10G TCP and UDP Accelerator IP cores and FPGA card solutions built around them at the IEEE Extreme Computing Summit at MIT-Lincoln-Labs, MA. From Sep 25th-28th 2018 at Booth-13.

Conference Website: http://www.ieee-hpec.org/index.htm
The 9th Gen core in addition to Full TCP/UDP stack, also implements IP Fragmentation/defragmentation for the UDP which puts frames back in order after they are broken up by the routers and in the process get out of order when they are received that causes them to be discarded. Intilop's new solution takes care of this age old problem as well, a unique capability that no other UDP Accelerator offers. Also, the TCP-UDP Accelerators perform functions of firewall and other monitoring functions at full line rate, the security module performs port filtering, blocking, monitoring and related functions in FPGA hardware at full line rate thereby relieving CPU from these tasks. During network security processing, the CPU gets bogged down under high traffic rates, sometimes missing some 'Events'. CPU cycles saved can be used for other application functions.

40G Frag/Defrag soon to be released.

These TCP/UDP Accelerators and Solutions are available in Intel/Altera and Xilinx FPGA based boards

The 10G TOE has been in volume production for more than 9 years now and is deployed around the globe interoperating with scores of different versions of TCP-UDP software stacks in a variety of networking equipment.

A sample of their TCP and UDP Accelerators can be found also at Intel/Altera and Xilinx websites:
Altera/Intel: https://www.altera.com/products/design-software/embedded-software-developers/opencl/developer-zone/opencl-reference-platforms.html
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/br/br-intellectual-property-brochure.pdf
Xilinx: http://www.xilinx.com/esp/datacenter/data_center_ip.html

In Jan. 2009, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs. Since then, they have released 8 generations, from 1G to 40G/50G, of TCP/UDP Accelerators. Their 100-ns-latency MAC-TOE-UOE are considered a 'Gold Standard' by the industry experts.

The latency barrier of 100-nanoseconds and throughput of more than 1 G byte/s per port was set by them since their first 10G Series of TCP engines in 2011.

About Intilop Website: www.intilop.com

Intilop is a developer of advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA developer-integrator and total-system-solutions provider for Networking, Network Security, storage and Embedded Systems. They offer silicon proven semiconductor IPs with comprehensive hardware-software solutions.

Intilop to Showcase their 40G-10G TCP-UDP Acceleration Technology and Solutions at MIT's Lincoln Labs

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