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Variation In Low-Power FinFET Designs

BY: ANN STEFFORA MUTSCHLER, Aug. 30, 2018 – 

One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield.

While variation is generally well understood, there are more sources of variation at each new node and the effects are additive. Moreover, traditional solutions to this problem no longer work, and rising complexity makes it more difficult to model. As a result, chipmakers are being forced to look for alternative approaches than just guard-banding.

"There is a lot more variation with the smaller finFET process geometries, especially at 10nm and below, due to the shrinking node process and wire alignment of the various lithographic effects," said Mary Ann White, director of product marketing for automotive, low power and finFET implementation at Synopsys. "At ultra-low voltages the variation is more magnified, where waveform distortion also happens due to increased wire resistance and Miller effects (higher capacitance),"

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