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Gowin Announces RISC-V EAP and New distributor Alcom

Guangzhou, China, Aug. 20, 2018 – 

Gowin Semiconductor Corp., the leading programmable logic devices provider in China, today announces Industry Earlier Adopter Program of RISC-V microprocessor implementation of Gowin ARORA® Family, including FPGA programming bit-file of a system level reference design with RISC-V MCU core, AHB & APB Bus, Memory Control & Peripherals, as well as GW-2A development board as total solution.

RISC-V is an open specification of an Instruction Set Architecture (ISA). The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind, but without over-architecting for a particular microarchitecture style. Gowin Arora® Family GW-2A FPGA are designed to offer the best-in-class performance cost ratio FPGA. With abundant logic, high performance DSP resources, and high speed I/O, the family is optimized for co-processing to offload the application processor on intensive computation tasks, as well as neatly optimized as the direct host of embedded microprocessor, like RISC-V ISA MCU soft core. The Arora® family is also the first FPGA with embedded SRAM in the industry, which gives customers more useable I/O. Gowin Industry Earlier Adopter Program of RISC-V Microprocessor offers a total solution including,

  1. GW-2A FPGA Device Chip
  2. GW-2A FPGA Development Board Hardware, with Micro-USB Download/Debug Cable
  3. GW-2A FPGA programming bit-file of a system level reference design with RISC-V MCU core, AHB & APB Bus, Memory Control & Peripherals
  4. Gowin FPGA Design EDA Software Suite, including Gowin IP-Core-Generator, supplying a rich set of Verilog Design IPs of Memory Controller, Datapath, DSP, etc., for building customized peripherals and/or interfacing module to the RISC-V MCU System
  5. Software Tool Chain (C-Code Compiler, Linker, Debugger) as well as RSIC-V MCU peripheral Software drivers, and built-in libraries for customized C-Code development
  6. Click here to read more ...

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