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IP Cores, Inc. Announces One-Year Anniversary of the Delivery of XTS4 Cores for the Server Memory Encryption

PALO ALTO, Calif. -- July 31, 2018 -- IP Cores, Inc., (California, USA, http://www.ipcores.com) has announced that the first shipment of the server memory encryption IP cores occurred one year ago.

“Our XTS4 FE/BE core family is designed for the memory encryption of a high-end computer server,” said Dmitri Varsanofiev, CTO of IP Cores, Inc., “These silicon-proven and CAVP-validated cores were designed for very high throughput at the clock frequencies of 2-3 GHz and above in the advanced semiconductor processes and are now available for shipments off-the-shelf.”

XTS4 Memory Encryption Cores

The cores implement the AES algorithm according to FISP-197 (https://nvlpubs.nist.gov/nistpubs/fips/nist.fips.197.pdf ) in the XTS mode per NIST SP800-38E (see https://csrc.nist.gov/publications/detail/sp/800-38e/final ). The core interface special features to simplify the process of data encryption and decryption during the cache line fill and write operations.

About IP Cores, Inc.

IP Cores (http://www.ipcores.com) is a rapidly growing California company in the field of security, error correction, data compression, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for embedded, communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, MACsec 802.1AE, IPsec and SSL/TLS protocol processors, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure cryptographic hashes (SHA-1/MD5, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), lossless data compression cores, low-latency and low-power fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi forward error correction (FEC) decoder cores.

All mentioned trademarks and registered trademarks are the property of their respective owners. CAVP is the Cryptographic Algorithm Validation Program run by NIST that provides validation testing of FIPS-approved and NIST-recommended cryptographic algorithms and their individual components, see https://csrc.nist.gov/Projects/Cryptographic-Algorithm-Validation-Program.

IP Cores, Inc. Announces One-Year Anniversary of the Delivery of XTS4 Cores for the Server Memory Encryption

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