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IMEC, Soitec stack device layers

Jul. 24, 2018 – 

This vertical integration of sequentially process device layers, also named sequential-3D integration (S3D), is seen as a promising alternative to lateral scaling.

The most critical challenge of sequential-3D-integration is managing the thermal budget and to avoid degrading circuits and interconnects in the bottom device layer the top device layer has to be processed at temperatures below 525 degrees C. This challenge has been overcome by using junction-less transistors in the top layer, which decreases fabrication complexity and the need for high temperature processing.

The top-tier device was processed at a temperature below 525 degree C achieving good device performance without impact from layer transfer (SS = 72mV/dec, DIBL = 80mV/V, Ioff = 1pA/micron, Ion=220microA/micron at VDD=1V).

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