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5nm Design Progress


Improvements in power, performance and area are much more difficult to achieve, but solutions are coming into focus.

Jul. 17, 2018 – 

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome.

Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, methodologies, and pre-developed blocks to make all of this work. But 5nm adds some new twists, including the insertion of EUV lithography for more critical layers, and more physical and electrical effects that could affect everything from signal integrity and yield to aging and reliability after manufacturing.

"For logic, the challenge at 5nm is to properly manage the interaction between the standard cells and the power grid," said Jean-Luc Pelloie, a fellow in Arm's Physical Design Group. "The days where you could build a power grid without considering the standard cells are over. The architecture of the standard cells must fit with the power grid implementation. Therefore, the power grid must be selected based on the logic architecture."

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