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USB 3.0 – A Cost Effective High Bandwidth Solution for FPGA Host Interface

Jun. 14, 2018 

Introduction

USB 3.0 has revolutionized the world of desktops and mobile devices by bringing much higher bandwidth and better power delivery compared to its predecessor USB 2.0. USB 3.0 (later renamed as USB 3.1 Gen 1) offers data rate of 5Gb/s or a whopping theoretical bandwidth of 625MB/s[1]. This is more than 10 times the theoretical maximum bandwidth of USB 2.0.[2] While practically available bandwidth for end user applications can be lower depending on the hardware and firmware solutions chosen(will discuss this later in this document), USB 3.0 offers a great value proposition that cannot be ignored. Other host interface solutions available in the market such as PCI Express, Thunderbolt and Ethernet can outperform USB 3.0 in many scenarios, but all these interfaces are relatively more expensive to implement especially in low volume segments. Also, USB 3.0 offers better power delivery compared to the other available solutions. This can further reduce the total cost of the solution/end product.

This whitepaper assumes a Xilinx FPGA is used in the solution. But the principles can be applied to most commercially available FPGA with certain exclusions.

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