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Cadence's Smarter and Faster Verification in the Era of Machine Learning, AI, and Big Data Analytics Panel


Jul. 11, 2018 – 

I attended on Monday, June 25, DAC's Opening Day, a Cadence-sponsored Lunch panel. Ann Steffora Mutschler (Semiconductor Engineering) was the Moderator and the Panelists were Jim Hogan (Vista Ventures), David Lacey (HP Enterprise), Shigeo Oshima (Toshiba Memory Corp), Paul Cunningham (Cadence).

In opening statements, Shigeo Oshima addressed the verification challenges seen by Toshiba Memory Corporation (TMC), that mirror the ones seen by most of the design community, as technology nodes are shrinking, and design size, complexity and costs are rising. He outlined the Cadence verification tools TMC is deploying to address those challenges.

Paul Cunningham stated what Cadence can do to address the current verification challenges, stressing that resources and headcount cannot continue to be squared in order to get to results. "We have many different engines at our disposal from traditional simulation, formal verification and different hardware with traditional simulation running on Intel x86, or ARM servers or custom processors or FPGAs and emulators and we are always looking to find out which engine to use in which case to maximize overall verification throughput. What can we do with ML, AI, how do we go off in this space efficiently? It does not feel efficient right now and we are burning millions of cycles in verification without making any difference in coverage or covering the same thing multiple times. There is a real opportunity to try to be more efficient to address this fundamentally intractable problem."

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