Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...

7nm, 5nm and 3nm Logic, current and projected processes

Jun. 25, 2018 – 

There has been a lot of new information available about the leading-edge logic processes lately. Papers from IEDM in December 2017, VLSIT this month, the TSMC and Samsung Foundry forums, etc. have all filled in a lot of information. In this article I will summarize what is currently known.

Process Metrics

Standard cells are used to design logic circuits and the size of standard cells is determined by Contacted Poly Pitch (CPP), Metal 2 Pitch (M2P) and Tracks (number of M2P in the cell height).

Click here to read more ...


Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.