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Samsung to introduce nanosheet transistors in 3nm node


Jun. 06, 2018 – 

Samsung Electronics has announced an update to its process node per year roadmap with the introduction of a 3nm gate-all-around (GAA) that will reportedly arrive some time in or after 2022. Above are 5nm nanosheet transistors reported by IBM at VLSI Technology Symposium in 2017.

The 3nm process comes in two variants – 3GAAE and 3GAAP – standing for early and plus and will be based on the nanosheet construction with multiple lateral ribbon-shaped wires in a fin. This nanosheet design has been much discussed by research institute IMEC as a follow-on to the FinFET and was researched by IBM in collaboration with Samsung and Globalfoundries.

"Applying GAA structure to our next generation process node will enable us to take the lead in opening a new smart, connected world, while also to reinforcing our technology leadership," said Charlie Bae, executive vice president and head of foundry sales and marketing at Samsung Electronics.

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