Block RAM integration for an Embedded FPGA

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May. 22, 2018 – 

The upcoming Design Automation Conference in San Francisco includes a very interesting session – "Has the Time for Embedded FPGA Come at Last?" Periodically, I've been having coffee with the team at Flex Logix, to get their perspective on this very question – specifically, to learn about the key features that customers are seeking to accelerate eFPGA IP adoption. At our recent kaffeeklatsch, Geoff Tate, CEO, and Cheng Wang, Senior VP Engineering, talked about a critical requirement that their customers have.

Geoff said, "Many of our customers are current users of commodity FPGA modules seeking to transfer existing designs into eFPGA technology, to leverage the PPA and cost benefits of SoC integration. One of the constituent elements of these designs is the use of the "Block RAM" memory incorporated into the commercial FPGA part. We had to develop an effective, incremental method to incorporate comparable internal RAM capabilities within the embedded FPGA IP. Flexibility is paramount, as well – we need to be able to accommodate different array types and configurations, with a minimal amount of our engineering team resources."

Figure 1. Illustration of the integration of memory array blocks in a vertical channel between eFPGA tiles.

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