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7nm SERDES Design and Qualification Challenges!

Nov. 22, 2017 – Semiconductor IP is the fastest growing market inside the fabless ecosystem, it always has been and always will be, especially now that non-traditional chip companies are quickly entering the mix. Towards the end of the year I always talk to the ecosystem to see what next year has in store for us and 2018 looks to be another year of double digit growth for IP companies, absolutely.



One of the more interesting conversations we have had (Tom Dillinger and myself) was with Analog Bits CEO Alan Rogers and EVP Mahesh Tirupattur. Analog Bits is well known for high performance and low power mixed-signal IP including SERDES which brings us to the most interesting part of our discussion and that is 7nm design and qualification challenges:

What are the major challenges for advanced node SERDES design?
"Starting with 28nm, we realized we had to re-think our design approach. We looked at our SERDES microarchitecture and layouts. We had to design the metal first, then the devices, then do our schematic based analysis. High-speed is a metal-dominated design." Click here to read more ...

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