Noesis Technologies releases its XTS mode AES processor IP Core

Jun. 15, 2017 – Noesis Technologies has announced today the immediate availability of its ntAES_XTS IP Core, a fully compliant core with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations targeting disk encryption applications at sector (data unit) addressable level. It is also known as a tweakable block cipher where the encryption process is controlled by the tweak a 128-bit value that is generated from the actual logical position of the data unit on the disk. This way identical data units stored at different places will result in different encrypted data thus addressing copy-and-paste attacks. Each data unit size is at least 128-bits. In addition each data unit size can be either an integral or non-integral number of 128-bit blocks. In case where the data unit size is not divisible with 128 then the ciphertext stealing procedure is used to enable correct encryption of the last block. Due to its highly parameterized and scalable architecture the users can trade off logic resources and performance in order to achieve optimum match with their application requirements. The implementation is low on latency, high speed with a simple interface for easy integration in SoC applications.

The ntAES_XTS can be used in applications such as single SATA 2.0 Hard Disk Drives (up to 3 Gbps throughput rate), single SATA 3.0 SSD (up to 6 Gbps throughput rate), USB 3.0 compliant storage, encrypted disk drives, SSDs for server arrays (up to 64 Gbps typical throughput rate) and encrypted memory sticks.

Availability

The ntAES_XTS is available under a flexible licensing scheme as parameterizable VHDL or Verilog source code or as a fixed netlist in various FPGA target technologies.

About Noesis Technologies P.C. (www.noesis-tech.com)

Noesis Technologies, P.C. is a silicon IP provider specialized in hardware implementation of high computational complexity telecom algorithms. Our hardware accelerator IP solutions allow telecom system developers to significantly off load demanding tasks from the CPU and to drastically decrease execution time thus boosting the overall system performance. Our IP cores present an industry leading combination of high performance, low power and low die-area, as well as easy customization for adaptability to a wide range of applications. Noesis offers a complete portfolio of Forward Error Correction IP core solutions that includes Reed Solomon Codecs, Viterbi Decoders, Turbo Product and Turbo Convolutional Codecs, LDPC Codecs, BCH codecs, (De)Interleavers, Channel Emulators. The company additionally offers a range of cores in the areas of security, networking, audio/voice compression and telecom DSP. Noesis Technologies is an expert in OFDM transmission technology and offers PHY layer IP Cores for wireless and wireline communications. Our turn-key solutions have been integrated in our customers' end-products in telecom, aerospace and defense systems. Noesis Technologies is headquartered at Patras Science Park, GR 26504 Patras, Greece and has offices at San Jose, CA 95134, USA. For more information please visit www.noesis-tech.com

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