Codasip Joins RISC-V Foundation and Announces Availability of RISC-V Compliant Codix Processor IP

Brno, Czech Republic , Jan. 05, 2016 – 

January 5th, 2016, Brno, Czech Republic -- Codasip, an industry leading application specific processor (ASIP) vendor, today announced that it has joined with other industry leaders as a founding member of the RISC-V foundation to accelerate customer adoption of commercial implementations of RISC-V based processor designs. Additionally, Codasip announced it is making available versions of its Codix Processor IP that are compliant with the RISC-V specification - expanding its existing embedded processor IP offerings.

ASIPs offer an unmatched combination of power, performance, and flexibility by optimizing the embedded processor for its target application. This is done by adapting the processors Instruction Set Architecture (ISA) and microarchitecture (how the processor responds to the ISA), and can lead to orders of magnitude improvements in power and performance.

Codasip's highly automated technology has made ASIP technology as accessible as standard embedded processors, allowing customers to create a processor ISA from scratch, or to use an existing ISA. The availability of RISC-V, with its support for extensibility, provides a great starting point for customers, combining the advantages of Codasip's proven technology and the open RISC-V ecosystem.

"One of the biggest challenges for customers new to ASIP technology is availability of a strong ISA they can build on," said Karel Masarik, CEO of Codasip. "Codasip's tools allow the creation of processors with any ISA and microarchitecture. By supporting RISC-V we leverage this powerful open initiative in order to accelerate our customers a path to a completed ASIP. At the same time, we provide the assurance of a commercially supported solution. It has always been Codasip's policy to build on open standards wherever possible, and so support for RISC-V builds on this product strategy."

In addition to ensuring that Codasip tools work seamlessly with the RISC-V specification (alongside customer specific enhancements), Codasip will also be making available RISC-V compatible versions of its Codix Processor IP. These cores will join the existing Codix implementations spanning ultralow-power to high performance with both RISC and VLIW implementations.

As with all Codix Cores, Codasip's RISC-V compliant cores are delivered using the high level processor description language CodAL, which allows customers to easily modify, adapt, and extend every aspect of the processor. Using this model, the complete LLVM/GNU based SDK, QEMU emulation model, RTL and verification environment is automatically generated. The result is unmatched flexibility, seamless integration of customer specific changes, and compatibility with the rich and evolving RISC-V ecosystem.

If you are interested in learning more about Codasip and our RISC-V offerings, you can connect with our technical team at the RISC-V workshop (Jan 5th & 6th - Oracle Conference Center in Redwood Shores, CA), visit our booth at Embedded World (Feb 23rd to 25th - Booth #620, Hall 4 - Nuremberg, Germany) or visit our website at www.codasip.com

About Codasip

Codasip delivers leading-edge technology that enables adoption of Application Specific Instruction-set Processors (ASIPs). ASIP's utilize dedicated instructions/architecture to accelerate software and are at the heart of applications that require very high performance with low power. Codasip's unique technology makes ASIP adoption as simple and easy as standard embedded processor cores. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe. More information on Codasip's products and services is available at www.codasip.com.

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