Arm Upgrades Interconnect, Memory Control IP

Peter Clarke-LONDON, Oct. 27, 2015 – 

Arm has upgraded its Corelink CCI coherent interconnect technology and digital memory controller as the basis for future heterogeneous system chips.

The Corelink CCI-550 provides 1 to 6 ACE interfaces and 1 to 6 memory interfaces, as compared with the maximum four of each provided by the CCI-500. The Corelink supports "big-little" processing and connection to a fully coherent GPU while increasing peak throughput.

The Corelink CCI-550 provide up to a 60 percent bandwidth increase as well as enhancements that reduce latency. An integrated and improved snoop filter function can save hundreds of milliwatts of power consumption, Arm claims.

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