Developing high-reliability FPGAs for DO-254

Can you bet your life on your designs?

by Louie De Luna, Aldec DO-254 Program Manager, Sept. 23, 2015 – 

You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization. You can visualize your timing diagram like you can visualize your upcoming vacation in Hawaii. You can manually write down your memory mapping accurately while under oath. You can pinpoint all CDC paths and emulate metastability in your mind. You are confident that your designs are fault-tolerant and will function as intended. You are the master of your domain.

But... can you bet your life on it?

Are you willing to bet your life on your designs? What about the lives of the thousands of passengers sitting on the airplanes where your FPGA design is installed? How certain are you that it won't fail in the field? If it were to fail, can it resume normal operation safely and timely? Not just MOST of the time, but EVERY time?

An FPGA installed on commuter aircraft systems with DAL A criticality level has 10 probability of failure per flight hour. A failure of DAL A FPGA is classified as Catastrophic Failure Condition, in which a failure prevents the safe flight and landing of the aircraft resulting in fatalities of all occupants. The FAA calls this "Extremely Improbable". The FAA further requires that "no single failure will result in a Catastrophic Failure Condition."

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