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Active Texts: The Swiss Army Knife of the schematic editor SLED!

by Dolphin Integration, Jul. 01, 2015 – 

It is commonplace that suppliers of EDA simulators allow configuring the testbench from some schematic editor. Meanwhile, a gap in terms of functionalities remains between configuring the testbench from the schematic versus from the simulator control file. To fill this gap, and to avoid restraining simulator usage without losing the focus on the schematics, Dolphin Integration provides the "Active Text" feature, an elegant approach to defining smart simulation features inside the schematic editor SLED™.

SLED allows circuit designers to perform graphic entry and to configure their designs in a shorter time. The flexibility of SLED enables the design of true mixed-signal circuits as well as multi-level and multi-physics systems.

In order to facilitate development, SLED 2.3 notably improves the capability of the schematic editor interaction with the simulator through the "Active Text" feature. The multi-purpose nature of the "Active Text" answers almost any functionality accessible through the netlist.

The four main assets of "Active Text" are:

These "Active Texts" are text entry areas that are placed in schematics and which content can be freely edited by the user. These texts are integrated into the files generated by the netlister. There are two types of "Active Texts" symbols: "Control Active Texts" and "Netlist Active Texts".

With "Control Active Texts", designers can add directives and simulation options (see Figure 1) for test benches configuration. The related texts are placed in the simulator control file.

It is then possible to define language instructions inserted into the generated netlist with "Netlist Active Texts" added in the schematic sheet. "Netlist Active Texts" support multiple languages (Spice, Verilog and VHDL) and can be used in an HDL module or a Spice subcircuit. They enable high flexibility and innovative design methodologies. For instance, in a Verilog module, the designer can add specific lines in different sections for adding Verilog processes or dynamically updating a module (see Figure 2).

An ADC test bench helps understanding the flexible and multi language approach enabled by "Active Texts". Analog designers sometimes need to perform signal processing measurements for validating their designs. For instance, an ADC integration verification requires Fast Fourier Transform (FFT), post-processing on the digital output for computing the Signal to Noise Ratio (SNR) and Total Harmonic Distortion (THD). With "Active Texts", the designer can create a checker symbol and a schematic in which an Active Text Control with a dedicated .MEASURE directive is placed (see Figure 3).

With correct parameterization of the "Active Text" (in this example: Language: SPICE, position: Pre sub-ckt body), the designer develops a "Reusable Hierarchical Checker" dedicated to detect ADC issues. As illustrated in Figure 4, SLED netlists a sub circuit called Checker with .MEASURE directives. Thus, with the schematic editor, the analog team can build custom libraries used for in-depth analysis. In brief, the"Active Text" feature provides high flexibility for interaction with the simulator and enables developing innovative design methodologies.

Moreover, to fully benefit from "Active Texts", SLED provides 2 additional features:

1) With "Back Annotation" (see Figure5), used to display the results of SMASH operatingpoints in SLED, designers can observe, depending on the back-annotation filter settings, the results of "Active Text" changes directly on the schematics.

2) With "Automatic Calculation" (see Figure 6), used for running simulations and displaying results in SLED automatically, designers can observe schematic changes written in the "Active Texts" directly in the waveform viewer (see Figure 7) and in the report page generated by "Automatic Calculation".

Simulation results and analysis are thus displayed by the schematic editor. This tool is very powerful and simple, leading to accelerating development and improving the quality of the design.

SLED 2.3 notably improves the capability to add simulation directives directly in the schematics. It contributes to reinforcing the link between SLED and SMASH. Designers can integrate simulator control directives into top-level schematics, paving the way to the setup of the test bench and the configuration of all simulations directly from the SLED schematic editor. The bundling of the schematic editor and a mixed-signal simulator like SLASH provides the perfect "Front-End Solution" for designing logic and mixed-signal Silicon IP and multi-physics systems.

For testing the best in class schematic editor SLED, do not hesitate to download it right here: http://www.dolphin.fr/index.php/eda_solutions/eda_downloads

For more information: contact@dolphin.fr

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