Arteris and YOGITECH Announce Strategic Partnership Enabling ISO 26262 Compliant Advanced Automotive Systems-on-Chip

Integration of Arteris FlexNoC Resilience Package and YOGITECH faultRobust technology enables more efficient ISO 26262 and ASIL compliance

CAMPBELL, California and PISA, Italy, Feb. 17, 2015 – 

Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions, and YOGITECH S.p.A., the leader in functional safety verification tooling and solutions, today announced a strategic partnership to help semiconductor design teams develop automotive and industrial systems-on-chip (SoCs) more effectively. The two industry-leading companies are teaming up to integrate their products to enable SoC vendors to more easily implement and assess functional safety requirements in complex chips.

The explosion of features developed in mobile phone and consumer electronics markets is now enabling new automotive features such as Advance Driver Assistance Systems (ADAS) and dedicated functional safety control units. As these automotive SoCs become larger and more complex, they are becoming harder to develop in accordance with ISO 26262 functional safety standards and to assess their compliance with automotive safety integrity levels (ASIL).

The Arteris and YOGITECH partnership will address these issues by providing SoC design teams:

• A quantitative and qualitative functional safety assessment of the Arteris FlexNoC interconnect IP and the FlexNoC Resilience Package
• A set of ISO 26262 deliverables for a series of SoC reference designs, which can then be used as a starting point in the preparation of ISO 26262 work products for Arteris FlexNoC Resilience Package users implementing custom designs
• An Arteris FlexNoC Safety Verification Component for use with the YOGITECH Safety Designer Tool Suite and the Safety Verifier Tool Suite.

YOGITECH and Arteris will extend this offering to the IEC 61508 standard, addressing safety-related industrial markets such as robotic systems.

“The fruits of this YOGITECH and Arteris partnership will help the automotive and semiconductor industries to more quickly implement in silicon the complex features required for autonomous driving systems,” said Silvano Motto, President and CEO of YOGITECH. “Using fRMethodology, designers can determine the best combination of hardware and software to achieve functional safety goals. Implementing functional safety features in silicon offers many advantages over software-only approaches by enabling less complexity, pre-characterized quality and more semiconductor vendor control over the system-wide functional safety feature implementations.”

“The Arteris FlexNoC Resilience Package has established itself as the easiest way to assemble complex automotive SoCs, and YOGITECH’s faultRobust technology is at the forefront of automating the functional safety verification of chips,” said K. Charles Janac, President and CEO of Arteris. “This combination of YOGITECH and Arteris technology will enable faster development of a new generation of smart automotive SoCs, with more advanced embedded vision, artificial intelligence and communications in our joint effort to support the goal of the self-driving car.”

About YOGITECH

YOGITECH S.p.A., based in Pisa, Italy, was founded in 2000 and is a leading provider of services and solutions to silicon vendors and system integrators to help them meet their functional safety challenges in different safety application domains like automotive, industrial, medical and railway.

About Arteris Inc

Arteris provides Network on Chip (NoC) interconnect IP to improve performance, power consumption and die size of system on chip (SoC) devices for consumer electronics, mobile, automotive and other applications.

Using Arteris solves pain for our customers. Traditional bus and crossbar interconnect approaches create serious problems for architects, digital and physical designers, and integrators: Massive numbers of wires, increased heat and power consumption, failed timing closure, spaghetti-like routing congestion leading to increased die area, and difficulty making changes for derivatives.

Whether you are using AXI, OCP, AHB or a proprietary protocol, Arteris Network on Chip (NoC) IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan. Having the option to configure each connection s width, and each transaction s dynamic priority, assures meeting latency and bandwidth requirements. And with the Arteris IP configuration tool suite, design and verification can be done easily, in a matter of days or even hours.

Arteris invented Network on Chip technology, offering the world s first commercial solution in 2006. Arteris connects the IP blocks in semiconductors from Qualcomm, Samsung, TI, and others, representing over 50 System on Chip devices. Find out more about Arteris products.

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