www.design-reuse-embedded.com
Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...

Small is Beautiful - How UVM Test Case Extraction Can Improve Your Constraint Analysis Productivity

by Axel Scherer - Cadence Blog, Jan. 28, 2015 – 

In the world formerly known as microelectronics, which is now actually nanoelectronics, small is sure beautiful. With the continued reduction in transistor size, we can afford to pack an insane amount of functionality into chips such as SoCs, while die sizes still remain tiny.

The amount of functionality on a modern SoC is truly mind-boggling. Even when you deal with a subsystem, you drown in complexity and excess information.

This can be particularly problematic in verification. Assume you are trying to stimulate your subsystem or complex block. You are very likely to use constrained random simulation with UVM. The problem is that the DUT complexity will make your constraints complex as well. This means that you need to produce a complex set of traffic into and out of the DUT.

In some cases, you might not be able to solve all the required constraints in your head. This will make it hard to predict the expected outcome, and what you should do about it.


Click here to read more...

 Back

Partner with us

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.